1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
2. Description of Related Art
An interlayer dielectric film used in manufacturing a semiconductor device may be composed of a plurality of films. Such an interlayer dielectric film is disclosed in Japanese Laid-open patent application HEI 4-218947. For example, an interlayer dielectric film may be composed of a base layer of a silicon oxide film, an SOG film disposed over the base layer, and a cap layer of a silicon oxide film disposed over the SOG film. The interlayer dielectric film may have a through hole formed therein. An internal wall of the through hole may be provided with a tapered section, such that a conductive film fills the through hole with good coverage.
In order to form the through hole having such a tapered shape, first, the interlayer dielectric film is selectively, isotropically etched, and the etching is stopped halfway. Due to the isotropic etching, the interlayer dielectric film is etched not only in a vertical direction, but also in a lateral direction. The closer to the upper surface of the through hole, the greater the through hole is etched in the lateral direction. As a result, the internal surface has a tapered section. Then, the etching is changed to an anisotropic etching to selectively etch the remaining interlayer dielectric film. By the steps described above, the through hole is completed.
It is noted that the etching speed for the SOG film is substantially greater than that for the cap layer. As a result, if the SOG film is isotropically etched, portions of the SOG film in the lateral direction are excessively etched. This creates recesses in the internal wall of the through hole.
Because of this reason, the isotropic etching is stopped in the cap layer, and thus the degree of freedom in conducting the isotropic etching is limited. As a consequence, for example, there are instances in which a conductive film may not fill a through hole having a relatively large aspect ratio.
It is an object of an embodiment of the present invention to provide a method for manufacturing a semiconductor device that improves the degree of freedom in isotropic etching and to provide a semiconductor device manufactured by the method.
In accordance with one embodiment of the present invention, a semiconductor device has a semiconductor substrate defining a main surface and an interlayer dielectric film located over the main surface, wherein the interlayer dielectric film includes a through hole having an upper surface section, a lower surface section and an internal surface having a tapered section between the upper surface section and the lower surface section.
In accordance with one embodiment of the present invention, the semiconductor memory device is manufactured by a method including at least the steps of: (a) reacting a silicon compound with hydrogen peroxide by a CVD method to form a first silicon oxide film that forms at least a part of the interlayer dielectric film; (b) reacting a silicon compound with at least oxygen or a compound including oxygen by a CVD method to form a second porous silicon oxide film that forms at least a part of the interlayer dielectric film and serves as a cap layer on the first silicon oxide film; and (c) selectively, isotropically etching the first silicon oxide film and the second silicon oxide film, to form a through hole that includes an internal surface having a tapered section, such that the through hole becomes smaller in a direction from the upper surface section toward the lower surface section.
A semiconductor device manufactured by a manufacturing method in accordance with one embodiment of the present invention has a semiconductor substrate defining a main surface and an interlayer dielectric film located over the main surface. The interlayer dielectric film includes a first silicon oxide film that is formed by reacting a silicon compound with hydrogen peroxide through a polycondensation reaction, and a second silicon oxide film that forms a cap layer and is located over the first silicon oxide film.
The interlayer dielectric film therefore includes a through hole that is formed in the first silicon oxide film and the second silicon oxide film and has an upper surface section, a lower surface section, and an internal surface between the upper surface section and the lower surface section. The internal surface includes a tapered section in such a manner that the through hole becomes smaller in diameter from the upper surface section toward the lower surface section.
In accordance with an embodiment of the present invention, the first silicon oxide film may be formed instead of an SOG film, in step (a). Preferably, the isotropic etching speed for the first silicon oxide film is the same or substantially the same as the isotropic etching speed for the second silicon oxide film. As a result, the first silicon oxide film can also be isotropically etched, and therefore, the degree of freedom in isotropic etching is improved.
The isotropic etching speed for the second silicon oxide film needs to be the same or substantially the same as the isotropic etching speed for the first silicon oxide film. The second silicon oxide film having such characteristics may be formed by a common CVD method, such as, for example, pyrolysis (thermal decomposition), and hydrolysis of a silane compound. The second silicon oxide film may be formed by a normal pressure CVD method, a plasma CVD method or a reduced pressure CVD method.
An impurity, such as, for example, phosphorous, boron or the like may preferably be added to the porous second silicon oxide film. More preferably, phosphorous is added to the second silicon oxide film. As a result the second silicon oxide film can relieve stresses by weakening the molecular bonding force between Si and O molecules of the silicon oxide that forms the film. As a result, the film becomes moderately soft and yet hard enough to be cracked. One of the roles of the second silicon oxide film is a function in which the impurity such as phosphorous contained in the silicon oxide film functions as a getter of mobile ions, such as alkali-ions that have deteriorating effects on the device element-reliability characteristics. The impurity concentration of the impurity contained in the second silicon oxide film may preferably be about 1-6 weight %, in consideration of the gettering function and the stress relieving function of the film.
Further, the second silicon oxide film has a function to prevent the first silicon oxide film from absorbing moisture. Also, the second silicon oxide film has an internal compression stress. Accordingly, when other films that form the interlayer dielectric film have internal tensile stresses, the second silicon oxide film alleviates the stresses and prevents the generation of cracks in the interlayer dielectric film.
A plasma CVD method for forming the second silicon oxide film may preferably be conducted with a high frequency at temperatures of about 300-450xc2x0 C. This step is effective in disconnecting water content from the first silicon oxide film.
The compound including oxygen that is used to form the second silicon oxide film may be oxygen (O2). However, more preferably, nitrogen monoxide (N2O) may preferably be used as the compound including oxygen to form the second silicon oxide film. By the use of nitrogen monoxide as a reactant gas, the nitrogen monoxide in a plasma state likely reacts with a hydrogen bond (xe2x80x94H) of the silicon compound that forms the first silicon oxide film. As a result, disconnection of gasification components (hydrogen, water) from the first silicon oxide film is promoted even while the second silicon oxide film is being formed.
Alternatively, a normal pressure CVD method at temperatures of about 300-550xc2x0 C. may be conducted to form the second silicon oxide film, instead of the plasma CVD method. In this case, ozone may be used as a compound including oxygen to form the second silicon oxide film.
Also, before the second silicon oxide film is formed, the first silicon oxide film may preferably be exposed to an ozone atmosphere. Since ozone likely reacts with a hydrogen bond (xe2x80x94H) and a hydroxyl (xe2x80x94H) of the silicon compound that forms the first silicon oxide film, this step promotes disconnection of hydrogen and water from the first silicon oxide film.
The thickness of the second silicon oxide film is preferably about 100 nm or greater in consideration of the planarization, prevention of cracks and the thickness of the interlayer dielectric film.
In accordance with one embodiment of the present invention, the first silicon oxide film may be formed by reacting a silicon compound and hydrogen peroxide through a CVD method. As a result, the formed interlayer dielectric film has an excellent planarization characteristic. More specifically, the first silicon oxide film thus formed has a high flowability itself and a high self-planarization characteristic. This phenomenon is believed to take place due to the following mechanism. When a silicon compound and hydrogen peroxide are reacted by the CVD method, silanol is formed in a vapor phase, and the silanol deposits on the surface of the wafer, thereby providing a film having a high flowability.
For example, when monosilane is used as a silicon compound, silanol is formed by reactions defined by formulas (1) and (1)xe2x80x2 as follows:
SiH4+2H2O2xe2x86x92Si(OH)4+2H2xe2x80x83xe2x80x83Formula (1)
SiH4+3H2O2xe2x86x92Si(OH)4+2H2O+H2xe2x80x83xe2x80x83Formula (1)xe2x80x2
Silanol formed by the reactions defined by Formulae (1) and (1)xe2x80x2 becomes silicon oxide as a result of disconnection of water by a polycondensation reaction defined by Formula (2) as follows:
Si(OH)4xe2x86x92SiO2+2H2Oxe2x80x83xe2x80x83Formula (2)
The silicon compounds include, for example, inorganic silane compounds, such as monosilane, disilane, SiH2Cl2, SiF4, and organic silane compounds, such as CH3SiH3, dimethylsilane, tripropyle-silane, tetraethylorthosilicate and the like.
The film formation in step (a) described above may preferably be conducted by a reduced pressure CVD method at temperatures of about 0-20xc2x0 C. when the silicon compound is an inorganic silicon compound, and at temperatures of about 0-150xc2x0 C. when the silicon compound is an organic silicon compound. If the temperature during the film-forming step is higher than the upper limit of the above-described temperature ranges, the polycondensation reaction defined by Formula (2) progresses excessively. As a result, the flowability of the first silicon oxide film lowers and therefore it is difficult to obtain good planarization. On the other hand, if the temperature is lower than the lower limit of the above-described temperature ranges, the control of a film forming apparatus becomes difficult. For example, adsorption of formed water content occurs within the chamber and dew condensation occurs outside the chamber.
The first silicon oxide film formed in accordance with one embodiment of the present invention may preferably be formed with a thickness that sufficiently covers step differences of the underlying layer. The minimum thickness of the first silicon oxide film depends on the height of protrusions and recesses of the underlying layer, and is preferably between about 300 and about 1500 nm. If the film thickness of the first silicon oxide film exceeds over the above-described upper limit, cracks may occur due to stresses of the film itself.
The manufacturing method may preferably include the step of annealing the interlayer dielectric film at temperatures of about 350-500xc2x0 C. between step (b) and step When the interlayer dielectric film includes a third silicon oxide film (base layer) that is located below the first silicon oxide film, the manufacturing method may preferably include the following step. Namely, the manufacturing method may preferably include, before step (a), the step of forming a third silicon oxide film by reacting a silicon compound with at least one of oxygen and a compound including oxygen by a CVD method.
The base layer has a passivation function that prevents migration of water and excess impurities from the first silicon oxide film to an underlying layer below the base layer (a main surface of a semiconductor substrate when there is no underlying layer). Also, the base layer has a function to increase the cohesiveness between the first silicon oxide film and an underlying layer below the base layer (a main surface of a semiconductor substrate when there is no underlying layer).
When a gettering effect is required to get alkali-ions, an impurity such as, for example, phosphorous in the amount of about 1-6 weight % may be added to the third silicon oxide film that forms the base layer. Alternatively, for example, a PSG film containing phosphorous in the amount of about 1-6 weight % may be formed between the third silicon oxide film and the first silicon oxide film.
In the manufacturing method in accordance with one embodiment of the present invention, step (c) may include the steps of selectively, isotropically etching the first silicon oxide film and the second silicon oxide film to form an upper section of the through hole that includes the tapered section, and selectively, anisotropically etching the interlayer dielectric film located below the upper section to form a lower section of the through hole. The upper section of the through hole may or may not reach the third silicon oxide film. In other words, the border between the upper section and the lower section of the through hole may be located at a position where the third silicon oxide film is formed, or at a position where the first silicon oxide film is formed. The through hole formed in the interlayer dielectric film of the semiconductor device is thus composed of the lower section and the upper section that is located above the lower section and includes the tapered section.
In accordance with one embodiment of the present invention, the manufacturing method may preferably include, after step (c), the step of forming a barrier layer that becomes a part of a wiring on surfaces of the through hole and the interlayer dielectric film, and the step of forming a conductive film that becomes a part of the wiring on surfaces of the barrier layer.
In one embodiment of the present invention, the interlayer dielectric film in the semiconductor device has a through hole. The semiconductor device further includes a barrier layer that becomes a part of a wiring that is formed on surfaces of the through hole and the interlayer dielectric film, and a conductive film that becomes a part of the wiring on surfaces of the barrier layer.
In accordance with one embodiment of the present invention, the conductive film may preferably be formed by the following steps. A first aluminum film composed of aluminum or an aluminum alloy containing aluminum as a main component is formed in the through hole at temperatures of about 200xc2x0 C. or lower, and then a second aluminum film composed of aluminum or an aluminum alloy containing aluminum as a main component is formed at temperatures of about 300xc2x0 C. or higher.
The alloy containing aluminum as a main component may be a two-component or a three-component alloy containing at least one of copper, silicon, germanium, magnesium, cobalt, beryllium and the like.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.